1. Field of the Invention
The present invention generally relates to a clock data recovery (CDR) circuit, and more particularly, to a frequency detection circuit and a detection method for a CDR circuit.
2. Description of Related Art
Generally, in order to correctly fetching data, a clock signal should be provided so as for being accorded to for sampling the data at a receiving terminal of a high speed serial data. The frequency and the phase of the clock signal must lock the received data signal. A conventional receiving terminal provides such a clock signal by a CDR circuit.
FIG. 1 is a schematic diagram of a conventional CDR circuit 100. Referring to FIG. 1, there is shown a voltage control oscillator (VCO) 103 providing a clock signal CLK. A phase detector 101 samples a data signal DS according to the clock signal CLK, and provides an instruction signal IS according to the sampling value. A charge pump 102 controls the VCO 103 to adjust a frequency of the clock signal CLK according to a status of the instruction signal IS.
FIGS. 2A through 2C schematically illustrate the operation of the phase detector 101. Referring to FIG. 2A, DS[0] through DS[3] represent four data transmitted by the data signal DS, in which there is a status change between each two data. The phase detector 101 consecutively samples the data signal DS according to the clock signal CLK, and provides the instruction signal IS according to a result of a comparison between the consecutive sampling values. As shown in FIG. 2A, if the sampling value 201 is equal to the sampling value 202, the two sampling values are all DS[1]. In this case, the phase detector 101 provides an instruction signal IS with a frequency reduction status, indicating that the frequency of the clock signal CLK is too high and should be reduced. If the sampling value 202 is equal to the sampling value 203, the two sampling values are all DS[2]. In this case, the phase detector 101 provides an instruction signal IS with a frequency boosting status, indicating that the frequency of the clock signal CLK is too low and should be boosted.
FIG. 2B illustrates a correlation of a status change time of the data signal DS with the status of the instruction signal IS, and the sampling time 202. If the clock signal CLK is too slow, the sampling time 202 is going to move rightwards, and therefore the instruction signal IS presents a frequency boosting status to accelerate the clock signal CLK, so as to have the sampling time 202 to move leftwards. Otherwise, if the clock signal CLK is too fast, the sampling time 202 is going to move leftwards, and therefore the instruction signal IS presents a frequency reduction status to decelerate the clock signal CLK, so as to have the sampling time 202 to move rightwards. In such a way, the sampling time 202 can be maintained at where the data signal DS changes status, i.e., a joint of two data, so as to guarantee the clock signal CLK to have a correct phase. FIG. 2C is another form of FIG. 2B.
The CDR circuit 100 is adapted for tracking the phase of the data signal DS, and is capable of tracking when there is a little difference between the frequencies of the data signal DS and the clock signal CLK. However, the CDR circuit 100 unfortunately can do nothing a large difference between the frequencies of the data signal DS and the clock signal CLK, which can be learnt by referring to FIG. 2B or 2C. In such a way, in order to prevent jitters, a conventional CDR circuit is usually featured of a very slight adjustment to the clock signal CLK, and thus incapable of tracking the frequency of the data signal DS which having a large difference.
In order to solve the problem, a dual-loop CDR circuit (also known as quadricorrelator) is proposed. FIG. 3 illustrates such a CDR circuit 300. The CDR circuit 300 includes a loop of a phase detector 301, and a charge pump 302 for phase detection, and a loop of a frequency detector 305 and a charge pump 306 for frequency detection. A VCO 303 provides two clock signals I_CLK and Q_CLK. A frequency of the clock signal I_CLK is same with that of the clock signal Q_CLK, while a phase of the clock signal Q_CLK falls π/2 behind a phase of the clock signal I_CLK. The phase detector 301 is functionally similar to the phase detector 101. Briefly, as shown in FIG. 4A, the phase detector 301 is adapted to sample the data signal DS according to the clock signal I_CLK, and provide a phase instruction signal PIS according to a result of the comparison between the consecutive sampling values. The charge pump 302 emits a control signal to the VCO 303, according to a status of the phase instruction signal PIS. The frequency detector 305 is functionally similar with the frequency detector 301. As shown in FIG. 4A, the frequency detector 305 is adapted to sample the data signal DS according to the clock signal Q_CLK, and provide a frequency instruction signal FIS according to a result of the comparison between the consecutive sampling values. The charge pump 306 emits a control signal to the VCO 303, according to a status of the frequency instruction signal FIS. An adder 304 is provided to add the control signals of the charge pumps 302 and 306, and output a final control signal to the VCO 303, for adjusting the frequencies of the clock signals I_CLK and Q_CLK.
FIG. 4B illustrates a correlation between the sampling times of the two clock signals and the statuses of the two instruction signals. As shown in FIG. 4B, when the frequencies of the clock signals I_CLK and Q_CLK are too fast, the phase instruction signal PIS changes its status prior to the frequency instruction signal FIS, as shown in FIG. 4C. On the contrary, when the frequencies of the clock signals I_CLK and Q_CLK are too slow, the frequency instruction signal FIS changes its status prior to the phase instruction signal PIS, as shown in FIG. 4D. When dividing a circle composed by the statuses of the two instruction signals into four quadrants, a diagram as shown in FIG. 4E can be obtained. As shown in FIG. 4E, when the frequencies of the clock signals I_CLK and Q_CLK are too fast, the diagram moves anticlockwise, and when the frequencies of the clock signals I_CLK and Q_CLK are too slow, the diagram moves clockwise. Such four quadrants not only enable the CDR circuit 300 to track the phase of the data signal DS, but also enable the CDR circuit 300 to track the frequency of the data signal DS.
In order to solve the conflict of the two instruction signals which present opposite statuses, the charge pump 306 must provide an adjustment very much more than an adjustment provided by the charge pump 302. However, it is hard for the CDR circuit 300 to determine the difference between the adjustments of the two charge pumps. If the difference is too small, a tracking speed will be affected, while if the difference is too large, the system may be caused unstable. As such, a suitable adjustment difference can be determined only upon the analysis to any possible data pattern and the frequency of changing status.